George Bisbas (Georgios Bismpas)

A few words about me

I am a Senior Research Engineer at the Huawei Zurich Research Center, within the Computing Systems Lab. Until recently, I was a Post-Doctoral Research Associate in the Department of Computing at Imperial College London. My work lies at the intersection of high-performance computing (HPC), compiler design, and domain-specific languages. I focus on compiler intermediate representations (IRs) and automated cache-level optimizations for finite-difference (FD) stencil computations. My broader expertise spans cache and loop optimizations, code generation, performance portability, and parallel programming across shared- and distributed-memory systems. As both a researcher and developer, I am passionate about delivering impactful solutions that bridge cutting-edge compiler theory with real-world applications. I emphasize scalable code generation, performance engineering, and open-source leadership, often through collaborative, cross-disciplinary efforts. My goal is to advance the state of HPC software and compiler ecosystems while mentoring others to contribute to open, reproducible science.

Selected Projects

• Devito Project: See www.devitoproject.org for more details
• XDSL Project: See XDSL Project for more details

Research Interests

• Compiler IRs and transformations
• Cache and loop-level optimizations
• Code generation and performance portability
• Shared- and distributed-memory parallelism
• HPC benchmarking and reproducibility
• Domain-specific languages (DSLs) for scientific computing
• Performance Engineering

Selected Publications

• George Bisbas, Rhodri Nelson, Mathias Louboutin, Fabio Luporini, Paul H.J. Kelly, Gerard Gorman (2024). Automated MPI-X code generation for scalable finite-difference solvers. In 39th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Milano, Italy, 2025, pp. 689-701. [IEEE] [Available on Arxiv] [Presentation slides] [Poster] *Finalist for IPDPS'25 Open Source Contribution Award*
• George Bisbas*, Anton Lydike*, Emilien Bauer*, Nick Brown*, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jameson, Paul H.J. Kelly, Michel Steuwer, Tobias Grosser (2024). A shared compilation stack for distributed-memory parallelism in stencil DSLs. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3 (ASPLOS '24), Vol. 3. Association for Computing Machinery, New York, NY, USA, 38–56. [Paper available online] [Presentation Slides] [Poster] *equal contribution*
• George Bisbas, Fabio Luporini, Mathias Louboutin, Rhodri Nelson, George Bisbas, Gerard Gorman, Paul H.J. Kelly. (2020). Temporal blocking of finite-difference stencil operators with sparse "off-the-grid" sources. In 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Portland, OR, USA, 2021, pp. 497-506. [Paper available online] [Presentation Slides]

Work Experience

• Senior Research Engineer, Dec 2025 - Today
  Huawei, Zurich Research Center
• Post Doctoral Research Associate, May 2022 - Mar 2025, 2023
  Imperial College London

Education

• PhD in High Performance, Embedded and Distributed Systems, 2023
  Imperial College London
• MSc in Intelligent Systems - Methods of Computational Intelligence and Applications, 2019
  Aristotle University of Thessaloniki (AUTH)
• Dipl. Eng. in Electrical and Computer Engineering, 2017
  Aristotle University of Thessaloniki (AUTH)