About Me

Senior researcher and developer with 10 years of deep expertise in compiler design for high-performance computing (HPC) — spanning high-level DSL design and efficient compilation down to automated, HPC-ready code generation for scientific applications. Proven track record in scalable code generation, performance engineering, and open-source leadership. Experienced in cross-disciplinary collaboration and mentoring.

Research Interests

• High Performance Computing (HPC)
• Distributed Systems for LLM Training & Inference
• Computational Science
• Domain-specific Languages
• Compiler optimizations
• Parallel Programming
• Performance Engineering

Technical Skills

• Programming: Python, C, C++, MPI, OpenMP, CUDA, SYCL, OpenACC, Matlab (Expert); Julia, Java, Cilk, AVR/MIPS Assembly, Cerebras CSL (Proficient)
• Compiler/IR: MLIR, LLVM (familiar), Devito DSL, PyPTO (Huawei)
• HPC/DevOps/CI/CD: GitHub Actions, Travis, Jenkins, Slurm, PBS, Docker, Microsoft Azure, and HPC environments generally
• HPC Tooling: Intel VTune, Advisor, Trace Analyzer & Collector, NVIDIA Nsight (Compute, Systems), Likwid, documentation & tutorials

Application-Oriented Skills

• LLM Training & Inference Compiler Infrastructure: Compiler infrastructure enabling distributed training and inference (data, tensor, expert, sequence, and pipeline parallelism) of large-scale LLM models across multi-chip clusters — distributed computing abstractions, compiler IRs and lowerings, collective communication primitives (AllReduce, AllGather, ReduceScatter, etc.), DSL API design, and orchestration code generation.
• Seismic Imaging & Wave Propagation: High-fidelity seismic waveform simulation, inversion workflows, isotropic/acoustic/elastic/anisotropic/visco-acoustic/visco-elastic modeling, distributed-memory code generation, and temporal cache optimization within the Devito framework.
• Computational Science & Engineering: Scalable, production-quality software stacks (Devito, xDSL) and reproducible pipelines for PDE-based simulations supporting climate, fluid dynamics, and multiphysics modeling.
• 3D Point Cloud Processing: Density-based clustering, feature-preserving data reduction for computer graphics, digital reconstruction, and smart manufacturing.

Professional Experience

• Senior Research Engineer, Huawei Research Center Nov 2025 – Now

  Zurich, Switzerland

  • Compiler & runtime development for distributed training and inference on Ascend NPUs; contributing to Huawei's compiler ecosystem (PyPTO / simpler / pto-isa), building the multi-chip distributed communication stack that enables large-scale models (e.g. DeepSeek, MoE architectures) to train and serve across clusters of Ascend NPUs 910B/910C.
  • Designed and implemented distributed abstractions and compiler IRs/lowerings for collective communication primitives (AllReduce, Broadcast, AllGather, ReduceScatter, etc.) in PyPTO's DSL, runtime and ISA.
  • Contributed across the full compiler stack: DSL API design, distributed IR types and compiler passes, orchestration code generation, runtime integration, and performance benchmarking.
• Airman (Informatics), Hellenic Air Force May 2025 – Nov 2025

  Larissa, Greece

  Six-month mandatory military service as required by the Greek government.
• Post-Doctoral Research Associate, Imperial College London Jun 2023 – Mar 2025
  Post-Doctoral Research Assistant, Imperial College London May 2022 – Jun 2023
  PhD Student, Imperial College London Oct 2018 – Apr 2022

  Advanced compiler infrastructure and code generation for PDE-based applications; domain-specific optimizations and efficient distributed-memory parallelism; temporal cache blocking for sparse off-the-grid operators (up to 1.6× speedup); automated MPI code generation; unified compilation stack (XDSL/Devito) with MLIR-based pipelines. Also contributed (mostly supervising) an end-to-end framework bridging high-level DSLs with the wafer-scale Cerebras CSL architecture. PhD thesis: Automated cache optimizations of stencil computations for partial differential equations, supervised by Prof. P. H. J. Kelly.

• Research Assistant, Aristotle University of Thessaloniki Nov 2017 – Oct 2018
  DigiPro project: developed advanced Mean Shift clustering algorithms for 3D point cloud simplification in MATLAB and C/Cilk.

Teaching Experience

• Graduate Teaching Assistant, Imperial College London Nov 2018 – Oct 2022
  • Parallel Programming using MPI (ACSE-6)
  • Advanced Computer Architecture (COMP60001)
  • Compilers (COMP50006)
  • Performance Engineering (COMP60017)
  • Reasoning about Programs (COMP40006)
  • Second Year Laboratory (C++ Picture Processing / Pintos)
• DiRAC Training Course Mentor, UCL Nov 2023
  • Bash Shell, Version Control with Git, Principles of Software Engineering, Testing & Documenting Code, Principles of Code Scaling

Selected Projects

Compiler Infrastructure (Huawei)

• PyPTO: compiler for distributed LLM training/inference on Ascend NPUs. [My merged PRs]
• simpler: runtime for the PyPTO compiler stack. [My merged PRs]
• pto-isa: virtual ISA underlying the PyPTO stack. [My merged PRs]
• PTOAS: assembler/optimizer for the PyPTO stack. [My merged PRs]

Compiler Infrastructure (Devito / xDSL)

• Devito Project: DSL and compiler for finite-difference PDE solvers. [My merged PRs]
• XDSL Project: Extensible compiler framework built on MLIR. Lead Maintainer/Developer in xdslproject/devito. See xdslproject/xdsl. [My merged PRs]

Personal Projects

• GreekProphet — Owner / Developer / Maintainer 2026 – Now
  Probabilistic forecasting platform for the Greek Super League: a Monte Carlo-based forecasting engine with rating systems and score models for match outcomes and season trajectories, built end-to-end in Python (simulation engine, data pipelines, backend services, and deployment).

Publications

Conference Publications

• Nicolai Stawinoga*, David Katz*, Anton Lydike, Justs Zarins, Nick Brown, George Bisbas, Tobias Grosser (2026). An MLIR Lowering Pipeline for Stencils at Wafer-Scale. ASPLOS '26, Vol. 2, Article 1, 16 pages. (*equal contribution) [ACM] [arXiv]
• George Bisbas, Rhodri Nelson, Mathias Louboutin, Fabio Luporini, Paul H.J. Kelly, Gerard Gorman (2024). Automated MPI-X code generation for scalable finite-difference solvers. IPDPS 2025, Milano, Italy, pp. 689–701. 🏆 Finalist for IPDPS'25 Open Source Contribution Award. [IEEE] [arXiv] [Slides] [Poster]
• George Bisbas*, Anton Lydike*, Emilien Bauer*, Nick Brown*, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jameson, Paul H.J. Kelly, Michel Steuwer, Tobias Grosser (2024). A shared compilation stack for distributed-memory parallelism in stencil DSLs. ASPLOS '24, Vol. 3, pp. 38–56. (*equal contribution) [ACM] [arXiv] [Slides] [Poster]
• George Bisbas, Fabio Luporini, Mathias Louboutin, Rhodri Nelson, Gerard Gorman, Paul H.J. Kelly (2020). Temporal blocking of finite-difference stencil operators with sparse "off-the-grid" sources. IPDPS 2021, Portland, OR, USA, pp. 497–506. [IEEE] [arXiv] [Slides]

Workshop Publications

• Joao Speglich, Navjot Kukreja, George Bisbas, Atila Saraiva, Jan Hückelheim, Fabio Luporini, John Washbourne (2024). Optimizing wavefield storage with high-speed media. ESSA'24, IPDPSW. [Paper]

In Preparation / Submitted

• Mathias Louboutin, Fabio Luporini, Philipp Witte, Rhodri Nelson, George Bisbas, Jan Thorbecke, Felix J. Herrmann, Gerard Gorman. Scaling through abstractions – high-performance vectorial wave simulations for seismic inversion with Devito. [arXiv]
• Rhodri Nelson, Fabio Luporini, Mathias Louboutin, George Bisbas, Gerard Gorman. TheMatrix: An automated cross-platform benchmarking suite. Submitted to JOSS. [GitHub]

Selected Talks & Presentations

• HiPEAC 2025, Barcelona — A shared compilation stack for distributed-memory parallelism in stencil DSLs [Slides]
• PASC24 — A shared compilation stack for HPC stencil DSLs (Minisymposium) [Slides]
• SIAM CSE 2023 — Automated Temporal Blocking in the Devito Compiler (MiniSymposium) [Slides]
• OGHPC 2021 — Temporal blocking for wave propagation with sparse off-the-grid sources [Video]
• CPC21, Porto — Temporal blocking of finite-difference stencil operators with sparse "off-the-grid" sources [Slides]
• DSL-HPC 2020 — Temporal blocking of finite-difference stencil operators with sparse non-grid-aligned sources and receivers in Devito [Video]

Poster Presentations

• Rice Energy HPC 2024 — Automated MPI-X code generation for scalable finite-difference solvers [Poster]
• SC 2019 — Accelerating real-world stencil computations using temporal blocking: handling sparse sources and receivers [Poster]

Peer Reviewing

Conferences

• Supercomputing Conference (SC) — Reproducibility Committee Member (2024, 2025)
• Euro-Par 2025 — Program Committee Member
• ICPP — Poster Committee Member (2024); Program Committee (2021)
• JuliaCon Conference Proceedings — Reviewer
• IMPACT 2024 — Reviewer
• PPoPP 2020 — Artifact Evaluation Committee Member
• JupyterCon 2020 — Proposal Community Reviewer

Journals

• ACM Transactions on Parallel Computing — Reviewer (2025)
• The Journal of Supercomputing, Springer — Reviewer
• Future Generation Computer Systems, Elsevier — Reviewer

Education

• PhD in High Performance, Embedded and Distributed Systems 2023

  Imperial College London

  Thesis: Automated cache optimizations of stencil computations for partial differential equations [Online]
  Supervisor: Prof. P. H. J. Kelly (with F. Luporini, G. J. Gorman)
• MSc in Intelligent Systems — Methods of Computational Intelligence and Applications 2019

  Aristotle University of Thessaloniki (AUTH) — Grade: 9.59/10 (Distinction)

  Thesis: On developing and accelerating point cloud simplification methods [Online (GR)]
  Supervisor: Prof. N. P. Pitsianis
• Dipl. Eng. in Electrical and Computer Engineering 2017

  Aristotle University of Thessaloniki (AUTH) — Grade: 8.75/10 (Distinction)

  Thesis: Forecast demand using Extended Discrete Fourier Transform [Online (GR)]
  Supervisor: Prof. N. P. Pitsianis